Apparatus and method for error reduction in distributed quantum systems via fusing-and-decomposing gates

ABSTRACT

Apparatus and method for error reduction in distributed quantum computing via fusing-and-decomposing gates. For example, one embodiment of an apparatus comprises: a quantum module comprising a plurality of qubits; unitary generation logic to combine a group of quantum gates to form at least one unitary operation; decomposition logic to decompose the unitary operation into multiple alternative gate sequences comprising either exact gate sequences or approximate gate sequences; and selection logic to evaluate the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.

BACKGROUND Field of the Invention

The embodiments of the invention relate generally to the field of quantum computing. More particularly, these embodiments relate to error reduction in distributed quantum systems via fusing-and-decomposing gates.

Description of the Related Art

Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which:

FIGS. 1A-1F illustrate various views of an example quantum dot device, in accordance with one embodiment;

FIG. 2 illustrates one embodiment of a processor pipeline for processing quantum and non-quantum instructions;

FIG. 3 illustrates an embodiment of front-end circuitry of a processor for processing quantum and non-quantum instructions;

FIGS. 4A-B illustrate embodiments of a quantum-classical processor interface;

FIGS. 5A-B illustrate an example quantum circuit and program code to implement the quantum circuit;

FIGS. 6A-B illustrate an example in which quantum instructions are generated by a compiler, decoded into uops, and executed within a quantum execution engine;

FIG. 7 illustrates a method in accordance with one embodiment of the invention;

FIG. 8 illustrates one embodiment of a qubit index generator for addressing qubits within a quantum processor;

FIG. 9 illustrates a method for determining qubit index values for identifying qubits;

FIG. 10 illustrates an example of a system which decodes and corrects quantum errors;

FIG. 11 illustrates a typical quantum error correction cycle;

FIGS. 12A-B illustrates inter-module interconnections between quantum gates;

FIG. 13A illustrates unitary generation logic for fusing a plurality of quantum gates to form a unitary;

FIG. 13B illustrates decomposition logic to decompose a unitary into a plurality of alternative gate sequences;

FIGS. 14A-B illustrate arrangements of quantum gates for a plurality of qubits spanning modules;

FIG. 15 illustrates fuse-and-decompose logic to perform fuse-and-decompose operations on selected qubit partitions;

FIG. 16A illustrates timings associated with gate operations for a specific clock cycle;

FIG. 16B illustrates an example of the locations of the quantum operations (i.e. gates) that are performed during a given clock cycle; and

FIG. 17 illustrates a method in accordance with one embodiment of the invention.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention described below. It will be apparent, however, to one skilled in the art that the embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the underlying principles of the embodiments of the invention.

INTRODUCTION

A quantum computer uses quantum-mechanical phenomena such as superposition and entanglement to perform computations. In contrast to digital computers which store data in one of two definite states (0 or 1), quantum computation uses quantum bits (qbits), which can be in superpositions of states. Qubits may be implemented using physically distinguishable quantum states of elementary particles such as electrons and photons. For example, the polarization of a photon may be used where the two states are vertical polarization and horizontal polarization. Similarly, the spin of an electron may have distinguishable states such as “up spin” and “down spin.”

Qubit states are typically represented by the bracket notations |0

and |1

. In a traditional computer system, a bit is exclusively in one state or the other, i.e., a ‘0’ or a ‘1.’ However, qbits in quantum mechanical systems can be in a superposition of both states at the same time, a trait that is unique and fundamental to quantum computing.

Quantum computing systems execute algorithms containing quantum logic operations performed on qubits. The sequence of operations is statically compiled into a schedule and the qubits are addressed using an indexing scheme. This algorithm is then executed a sufficiently large number of times until the confidence interval of the computed answer is above a threshold (e.g., ˜95+%). Hitting the threshold means that the desired algorithmic result has been reached.

Qubits have been implemented using a variety of different technologies which are capable of manipulating and reading quantum states. These include, but are not limited to quantum dot devices (spin based and spatial based), trapped-ion devices, superconducting quantum computers, optical lattices, nuclear magnetic resonance computers, solid-state NMR Kane quantum devices, electrons-on-helium quantum computers, cavity quantum electrodynamics (CQED) devices, molecular magnet computers, and fullerene-based ESR quantum computers, to name a few. Thus, while a quantum dot device is described below in relation to certain embodiments of the invention, the underlying principles of the invention may be employed in combination with any type of quantum computer including, but not limited to, those listed above. The particular physical implementation used for qbits is orthogonal to the embodiments of the invention described herein.

Quantum Dot Devices

Quantum dots are small semiconductor particles, typically a few nanometers in size. Because of this small size, quantum dots operate according to the rules of quantum mechanics, having optical and electronic properties which differ from macroscopic entities. Quantum dots are sometimes referred to as “artificial atoms” to connote the fact that a quantum dot is a single object with discrete, bound electronic states, as is the case with atoms or molecules.

FIGS. 1A-1F are various views of a quantum dot device 100, which may be used with embodiments of the invention described below. FIG. 1A is a top view of a portion of the quantum dot device 100 with some of the materials removed so that the first gate lines 102, the second gate lines 104, and the third gate lines 106 are visible. Although many of the drawings and description herein may refer to a particular set of lines or gates as “barrier” or “quantum dot” lines or gates, respectively, this is simply for ease of discussion, and in other embodiments, the role of “barrier” and “quantum dot” lines and gates may be switched (e.g., barrier gates may instead act as quantum dot gates, and vice versa). FIGS. 1B-1F are side cross-sectional views of the quantum dot device 100 of FIG. 1A; in particular, FIG. 1B is a view through the section B-B of FIG. 1A, FIG. 1C is a view through the section C-C of FIG. 1A, FIG. 1D is a view through the section D-D of FIG. 1A, FIG. 1E is a view through the section E-E of FIG. 1A, and FIG. 1F is a view through the section F-F of FIG. 1A.

The quantum dot device 100 of FIG. 1 may be operated in any of a number of ways. For example, in some embodiments, electrical signals such as voltages, currents, radio frequency (RF), and/or microwave signals, may be provided to one or more first gate line 102, second gate line 104, and/or third gate line 106 to cause a quantum dot (e.g., an electron spin-based quantum dot or a hole spin-based quantum dot) to form in a quantum well stack 146 under a third gate 166 of a third gate line 106. Electrical signals provided to a third gate line 106 may control the electrical potential of a quantum well under the third gates 166 of that third gate line 106, while electrical signals provided to a first gate line 102 (and/or a second gate line 104) may control the potential energy barrier under the first gates 162 of that first gate line 102 (and/or the second gates 164 of that second gate line 104) between adjacent quantum wells. Quantum interactions between quantum dots in different quantum wells in the quantum well stack 146 (e.g., under different quantum dot gates) may be controlled in part by the potential energy barrier provided by the barrier potentials imposed between them (e.g., by intervening barrier gates).

Generally, the quantum dot devices 100 disclosed herein may further include a source of magnetic fields (not shown) that may be used to create an energy difference in the states of a quantum dot (e.g., the spin states of an electron spin-based quantum dot) that are normally degenerate, and the states of the quantum dots (e.g., the spin states) may be manipulated by applying electromagnetic energy to the gates lines to create quantum bits capable of computation. The source of magnetic fields may be one or more magnet lines, as discussed below. Thus, the quantum dot devices 100 disclosed herein may, through controlled application of electromagnetic energy, be able to manipulate the position, number, and quantum state (e.g., spin) of quantum dots in the quantum well stack 146.

In the quantum dot device 100 of FIG. 1 , a gate dielectric 114 may be disposed on a quantum well stack 146. A quantum well stack 146 may include at least one quantum well layer 152 (not shown in FIG. 1 ) in which quantum dots may be localized during operation of the quantum dot device 100. The gate dielectric 114 may be any suitable material, such as a high-k material. Multiple parallel first gate lines 102 may be disposed on the gate dielectric 114, and spacer material 118 may be disposed on side faces of the first gate lines 102. In some embodiments, a patterned hardmask 110 may be disposed on the first gate lines 102 (with the pattern corresponding to the pattern of the first gate lines 102), and the spacer material 118 may extend up the sides of the hardmask 110, as shown. The first gate lines 102 may each be a first gate 162. Different ones of the first gate lines 102 may be electrically controlled in any desired combination (e.g., each first gate line 102 may be separately electrically controlled, or some or all the first gate lines 102 may be shorted together in one or more groups, as desired).

Multiple parallel second gate lines 104 may be disposed over and between the first gate lines 102. As illustrated in FIG. 1 , the second gate lines 104 may be arranged perpendicular to the first gate lines 102. The second gate lines 104 may extend over the hardmask 110, and may include second gates 164 that extend down toward the quantum well stack 146 and contact the gate dielectric 114 between adjacent ones of the first gate lines 102, as illustrated in FIG. 1D. In some embodiments, the second gates 164 may fill the area between adjacent ones of the first gate lines 102/spacer material 118 structures; in other embodiments, an insulating material (not shown) may be present between the first gate lines 102/spacer material 118 structures and the proximate second gates 164. In some embodiments, spacer material 118 may be disposed on side faces of the second gate lines 104; in other embodiments, no spacer material 118 may be disposed on side faces of the second gate lines 104. In some embodiments, a hardmask 115 may be disposed above the second gate lines 104. Multiple ones of the second gates 164 of a second gate line 104 are electrically continuous (due to the shared conductive material of the second gate line 104 over the hardmask 110). Different ones of the second gate lines 104 may be electrically controlled in any desired combination (e.g., each second gate line 104 may be separately electrically controlled, or some or all the second gate lines 104 may be shorted together in one or more groups, as desired). Together, the first gate lines 102 and the second gate lines 104 may form a grid, as depicted in FIG. 1 .

Multiple parallel third gate lines 106 may be disposed over and between the first gate lines 102 and the second gate lines 104. As illustrated in FIG. 1 , the third gate lines 106 may be arranged diagonal to the first gate lines 102, and diagonal to the second gate lines 104. In particular, the third gate lines 106 may be arranged diagonally over the openings in the grid formed by the first gate lines 102 and the second gate lines 104. The third gate lines 106 may include third gates 166 that extend down to the gate dielectric 114 in the openings in the grid formed by the first gate lines 102 and the second gate lines 104; thus, each third gate 166 may be bordered by two different first gate lines 102 and two different second gate lines 104. In some embodiments, the third gates 166 may be bordered by insulating material 128; in other embodiments, the third gates 166 may fill the openings in the grid (e.g., contacting the spacer material 118 disposed on side faces of the adjacent first gate lines 102 and the second gate lines 104, not shown). Additional insulating material 117 may be disposed on and/or around the third gate lines 106. Multiple ones of the third gates 166 of a third gate line 106 are electrically continuous (due to the shared conductive material of the third gate line 106 over the first gate lines 102 and the second gate lines 104). Different ones of the third gate lines 106 may be electrically controlled in any desired combination (e.g., each third gate line 106 may be separately electrically controlled, or some or all the third gate lines 106 may be shorted together in one or more groups, as desired).

Although FIGS. 1A-F illustrate a particular number of first gate lines 102, second gate lines 104, and third gate lines 106, this is simply for illustrative purposes, and any number of first gate lines 102, second gate lines 104, and third gate lines 106 may be included in a quantum dot device 100. Other examples of arrangements of first gate lines 102, second gate lines 104, and third gate lines 106 are possible. Electrical interconnects (e.g., vias and conductive lines) may contact the first gate lines 102, second gate lines 104, and third gate lines 106 in any desired manner.

Not illustrated in FIG. 1 are accumulation regions that may be electrically coupled to the quantum well layer of the quantum well stack 146 (e.g., laterally proximate to the quantum well layer). The accumulation regions may be spaced apart from the gate lines by a thin layer of an intervening dielectric material. The accumulation regions may be regions in which carriers accumulate (e.g., due to doping, or due to the presence of large electrodes that pull carriers into the quantum well layer), and may serve as reservoirs of carriers that can be selectively drawn into the areas of the quantum well layer under the third gates 166 (e.g., by controlling the voltages on the quantum dot gates, the first gates 162, and the second gates 164) to form carrier-based quantum dots (e.g., electron or hole quantum dots, including a single charge carrier, multiple charge carriers, or no charge carriers). In other embodiments, a quantum dot device 100 may not include lateral accumulation regions, but may instead include doped layers within the quantum well stack 146. These doped layers may provide the carriers to the quantum well layer. Any combination of accumulation regions (e.g., doped or non-doped) or doped layers in a quantum well stack 146 may be used in any of the embodiments of the quantum dot devices 100 disclosed herein.

Apparatus and Method for a Hybrid Classical Quantum Computer

After Richard Feynman asked in 1982 whether quantum physics could be simulated efficiently using a quantum computer, much effort researching for a quantum computer has been focused on its universality and its efficiency over classical computation. One such example is David Deutsch's quantum Turing machine in 1985 that can be programmed to perform any computational task that can be performed by any physical object.

In contrast to theories and algorithms, quantum physical machines are in still their infancy. Efforts to build quantum information processing systems have resulted in modest success to date. Small quantum computers, capable of performing a small set of quantum operations on a very few qubits, represent the state of the art in quantum computation. In addition, quantum states are fragile in the sense that quantum states only remain coherent for a limited duration. This gap between algorithms and physical machines has driven the effort to invent hybrid classical-quantum algorithms. Some recent quantum algorithm developments have focused on short-depth quantum circuits to carry out quantum computations formed as subroutines embedded in a larger classical optimization loop, such as the variational eigensolver (P. J. J. O'Malley, 2016). Quantum languages, tools, and flows have been developed, providing software layers/stacks to translate and optimize applications to the quantum physical layer to cope with the stringent resource constraints in quantum computing (Frederic T. Chong, 2017, 14 September).

On the hardware side, classical computers have been used to perform error correction for quantum computations. The “quantum co-processor” model is the most favorable prevailing execution model where a classical CPU controls a quantum processing unit in a similar manner to how CPUs in modern computer systems interact with GPUs. As described in (X. Fu, 2016, May) and (X. Fu, 2018), the microarchitecture for experimental superconducting quantum co-processors included features such as an arbiter on the code fetch data path to steer classical instruction to host CPU and quantum instruction to quantum co-processor, an exchange register file to synchronize register files between host CPU and the quantum co-processor, and a quantum instruction cache.

The microarchitectures for these mechanisms, however, are not well defined and explicit support for hybrid classical-quantum programs is lacking. Consequently, it is unclear how a quantum co-processor would be implemented within a quantum computer, particularly one which is required to run a diverse set of quantum programs. A flexible and programmable model has yet to be developed for executing hybrid classical-quantum algorithms.

One embodiment of the invention adds a set of quantum instructions to an instruction set architecture (ISA) of a processor such as a CPU. By way of example, these instructions may be included in an extension to the ISA (e.g., such as the AVX-512 extensions for the x86 platform). In addition, in one embodiment, a quantum engine is added to the processor's execution unit and the new quantum instructions are fetched, decoded, scheduled, and executed on the functional units of the quantum engine. In one embodiment, the quantum engine interacts with the classical execution engines using a shared register file and/or system memory. Upon executing the quantum instructions (or quantum uops in certain embodiments described herein), the quantum execution engine generates control signals to manipulate the state of the qubits within the quantum processor. The quantum engine also executes instructions to take a measurement of specified sets of qubits and store the results. In these embodiments, a quantum/classical interface provides connectivity between the quantum engine of the classical processor and the quantum processor.

FIG. 2 illustrates one embodiment of a processor or core 210 which fetches, decodes, and executes quantum instructions 201A and non-quantum instructions 201B, utilizing the same pipeline resources as the non-quantum instructions 201B. The processor/core 210 of this embodiment supports quantum extensions to an existing ISA of the processor/core 210 (e.g., extending the ISA to include the quantum instructions 201A). Program code 205C comprising the quantum and non-quantum instructions is generated by a compiler 205B from source code 205A written by a programmer (e.g., utilizing the extended ISA). Various source/program code examples are provided below.

Quantum and non-quantum instructions 201A-B are fetched from memory 205 at the front end of the instruction pipeline and stored in a Level 1 (L1) instruction cache 201. Instructions and data may also be stored within a Level 2 or Level 3 cache within a cache/memory subsystem 215, which manages memory requests and cache coherency.

A decoder 202 decodes the instructions 201A-B into micro-operations or uops 203A which are scheduled for execution by a scheduler 203 and executed by execution circuitry 204. In one embodiment, certain stages of the pipeline are enhanced to include hardware support for processing the quantum instructions 201B while other stages are unaltered. For example, quantum decode circuitry 202A may be added to the decoder 202 for decoding the quantum instructions 201A, just as non-quantum decode circuitry 202B decodes non-quantum instructions 201B. Although illustrated as separate components in FIG. 2 for the purpose of explanation, the quantum decode circuitry 202A and non-quantum decode circuitry 202B may comprise a common or overlapping set of circuitry and/or microcode. For example, in one embodiment, an existing decoder may be extended to include microcode support for quantum instructions (e.g., in microcode ROM) to generate new sets of quantum uops. The decoder 202 includes other decode circuitry such as a set of decode table structures (see, e.g., FIG. 3 and associated text), depending on the processor architecture.

In one embodiment, the decoder 202 generates a sequence of uops 203A in response to decoding the instructions 201A-B. In an implementation with quantum and non-quantum instructions, the uops may include a mixture of quantum uops and non-quantum uops, which are then scheduled for execution by an instruction scheduler 203.

The quantum and non-quantum uops 203A generated by the decoder 202 may initially be queued for execution within one or more uop queues of the scheduler 203, which dispatches the uops from the uop queue(s) in accordance with dependencies and/or execution resource availability. The embodiments of the invention may be implemented on various different types of processors with different types of schedulers. For example, in one embodiment, a set of execution “ports” couple the scheduler 203 to the execution circuitry 204, where each execution port is capable of issuing uops to a particular set of functional units 204C-E. In the example architecture shown in FIG. 2 , for example, SIMD and floating point (FP) uops may be issued by the scheduler 203 over a FP/SIMD execution port coupled to a set of FP/SIMD functional units 204C and integer uops may be issued over an integer port coupled to a set of integer functional units 204D. While only two types of non-quantum functional units are shown for simplicity, the processor/core 210 may include various other/additional non-quantum functional units (e.g., such as load/store address generation units, branch units, additional SIMD and integer units, etc).

In the particular embodiment shown in FIG. 2 , the quantum engine functional units 204E share the same set of register files 204A-B used by the legacy processor functional units 204C-D. In this particular example, the register files 204A-B include a FP/SIMD register file 204A which stores floating point and SIMD operands used by the FP/SIMD functional units 204C and an integer register file 204B which stores integer operands for the integer functional units 204D. In one implementation, the FP/SIMD register file 204A comprises 512 bit vector registers and the integer register file 204B comprises 64-bit scalar registers. Of course, different processor architectures will use different types of registers shared by the quantum engine functional units 204E. Various other types of registers may also be used such as a set of control/status registers and mask registers.

In an embodiment in which quantum uops are mixed with non-quantum uops, the quantum uops are issued over one or more quantum ports to a set of quantum engine functional units 204E, which execute the quantum uops to perform the underlying quantum operations. For example, the quantum engine functional units 204E, in response to the quantum uops, may generate control signals over a quantum-classical interface 206 to manipulate and take measurements of the qubits of a quantum processor 207.

The quantum-classical interface 206 includes digital-to-analog (D-A) circuitry to convert the digital quantum control signals generated by the quantum engine functional units 204E to analog signals required to control the quantum processor 207 (e.g., such as the codeword triggered pulse generation (CTPG) units and Arbitrary Waveform Generator (AWG) described below) and also includes analog-to-digital (A-D) circuitry to convert the physical qubit measurements to digital result data.

In one embodiment, the quantum-classical interface 206 is integrated on the same semiconductor chip as the other components of the instruction processing pipeline (e.g., the execution circuitry 204, scheduler 203, decoder 202, etc). As discussed in detail below, different types of circuit/logic components may be used depending on the particular physical implementation of the quantum processor 207.

FIG. 3 illustrates one embodiment in which quantum instruction processing support is added to a low power processing pipeline including a pre-decode buffer 301B, a 2-way decoder 302 with dual sets of quantum/non-quantum decoder circuitry 202A-B, 302A-B, dual lookup tables for instruction translation (XLAT), and a ucode ROM 304. In one embodiment, the XLAT components 303, 305 and ucode ROM 304 are extended to support the quantum instructions, as indicated by logic blocks 303Q-305Q. The pre-decode buffer 301B detects and marks macro-instruction boundaries prior to full decoding into uops by the 2-way decoder 302.

The operands for the quantum and non-quantum uops are stored in a set of shared registers 321 (as described above) and accessed by the quantum functional units 320 when executing the uops. The Q-C interface 320, in response to the quantum uops, controls the operation of the quantum processor 207.

Different examples of a quantum-classical interface 206 are illustrated in FIGS. 4A-B. The Q-C interface 206 in FIG. 4A includes a plurality of uop units 401A-C which, responsive to the uops executed by the quantum engine functional units 204E, generate codewords to control operation of a plurality of codeword triggered pulse generation (CTPG) units 402A-C. In response, the CTPG units 402A-C generate sequences of pulses to control the qubits of the quantum processor 207. Once the quantum processor 207 has reached a specified execution state, quantum measurements are taken by one or more of the measurement discrimination units (MDUs) 403A-B.

The Q-C interface 206 shown in FIG. 4B includes a set of components to perform microwave complex signal generation including an RF microwave unit 451, multi-channel Arbitrary Waveform Generators (AWG) 452, one or more digital to analog converters (DACs) 453 and one or more measurement units 454. In one embodiment, the input to each of these components comprises a set of codewords generated by the quantum engine functional units 204E and the output is an analog waveform which manipulates the state of the qubits of the quantum processor 207. The measurement units 454 measure a current state associated with one or more qubits at a designated point in execution.

To further guide the analysis and discussion, a concrete example is illustrated in FIG. 5A, which shows a quantum circuit for a many-body disordered Hamiltonian to be time-evolved. Note that the angle through which R_(x) and R_(y) rotate are derived from several parameters. Particularly, hi and h_(k) ^(x) with k∈{0, 1, . . . , 5, 6} are randomly generated and are used to emulate large many-body systems that require many more number of qubits than what the underlying quantum chip supports.

One example of a quantum program that uses this circuit for a portion of its computation is illustrated in FIG. 5B which includes a mixture of quantum instructions and non-quantum instructions (as indicated by the comments to the right of the source code). In this example, NR is the number of disorder realizations (i.e. multiple small random realizations to emulate a large many-body system), NQ is the number of Qubits, NP is the number of iterations in order to achieve the required precision on Probability (Pr), NT is the number of Trotter steps, and a[i] accumulates Qubit measurement. The probability of qubits being in state |0> or |1> is obtained by repeating measurements (NP) and averaging.

This program structure shows how classical operations and quantum operations may be tightly intertwined and executed on the classical-quantum processing architectures described herein. The most efficient way to execute this program is to process all instructions in a pipeline such as those described above, with the quantum engine functional units 204E for controlling qubits configured as execution engine peer to other classical execution engines 204A-B (such as integer, floating point, etc.).

FIGS. 6A-B provide an example of the quantum operations performed in response to the program code in FIG. 5A. In particular, FIG. 6A illustrates a portion of quantum assembly language (QASM) code 601 to implement the highlighted portion 501 of the quantum circuit in FIG. 5A. The QASM code 601 is compiled into hybrid processor program code 602 in memory 205. In this example, the registers RBX and RBX+1 from the shared register file 321 or 204B are used to hold qubit indices to address logical qubits #2 and #3, respectively, in this particular example. The mapping of the relevant portions of the QASM code 601 to the hybrid processor program code 602 is indicated by arrows.

FIG. 6B illustrates how a quantum macroinstruction QCNOTUP (to implement a CNOT gate) is decoded into a series of uops 605 by the decoder 202. The uops 605 are executed by the quantum engine functional units 204E to generate codewords with a specified codeword or command packet format 606. In one particular format, a first data field indicates the qubit on which the operation is to be performed (qubit 3 in the example), a second data field indicates the channel over which the operation is to be transmitted (channel 4), a third field to indicate the command state (e.g., single command state), and a fourth data field to indicate the type of qubit (a transmon qubit). Of course, the underlying principles of the invention are not limited to any particular encoding format.

A method in accordance with one embodiment of the invention is illustrated in FIG. 7 . The method may be implemented within the context of the processor architectures described above but is not limited to any particular processor or system architecture.

At 701 source code containing quantum instructions is compiled to generate runtime program code with quantum and non-quantum instructions. At 702 the quantum/non-quantum instructions are fetched from memory and stored in a local cache (e.g., the L1 instruction cache) or instruction buffer. As mentioned, quantum instructions may be freely mixed with non-quantum instructions within the pipeline.

At 703 the quantum and non-quantum instructions are decoded into sets of quantum and non-quantum uops, respectively, and stored in a queue prior to execution. At 704 the quantum/non-quantum uops are scheduled for execution based on uop and/or resource dependencies. For example, if a first uop is dependent on the results of a second uop then the first uop may be scheduled for execution only when the data produced by the second uop is available in one of the registers. Similarly, if a particular functional unit is busy, then the scheduler may wait for an indication that the functional unit is available before scheduling a uop which requires that functional unit. Various other/additional scheduling techniques may be implemented (e.g., scheduling based on priority, register load, etc).

At 705 the quantum uops and non-quantum uops are executed on their respective functional units within the execution circuitry. As mentioned, the shared register set may be used to store the source and destination operands required by these uops.

At 706, the results generated by the execution of the quantum uops may be used as input to an interface unit to control the quantum state of the qubits in a quantum processor. In one embodiment, a series of codewords or command packets may be generated which identify a quantum channel, one or more qubits within a quantum processor, a qubit type and/or a command state. The specific physical operations performed in response to the codeword or command packet is based on the underlying type of quantum processor used.

The embodiments described herein integrates quantum instructions within an existing processor pipeline. Because of the tight integration, these embodiments significantly reduces the various overheads/bottlenecks associated with current co-processor designs. These overheads/bottlenecks include, for example, the communication between the classical computation layers/modules and the quantum computation layers/modules in the software stack and between the classical CPU and the quantum chip via the message queue. Given the relatively small size of quantum routines, the current GPU-like co-processor implementations are inefficient.

Due to increased classical processing capabilities, hybrid co-processor models reduce some of the overhead. In one particular implementation which supports the hybrid co-processor model, many new micro-architecture mechanisms were introduced. However, these micro-architectural mechanisms were ambiguously defined as was the boundary between the classical CPU and quantum co-processor.

In contrast, in the hybrid architecture described herein, the classical computation pipeline is equipped to fully support a defined set of quantum instructions which may be freely mixed with non-quantum instructions both at the front end of the pipeline (i.e., at the macroinstruction level) and within the back-end of the pipeline (e.g., where quantum uops are mixed with non-quantum uops) and executed on functional units within the execution circuitry of the processor.

Scalable Qubit Addressing Mode for Quantum Execution Engine and/or Co-Processor

In quantum computing, a qubit is a unit of quantum information which is the quantum analogue of a classical binary bit. The computation is achieved by applying quantum gates, representing quantum logical operations, directly to qubits. Mathematically, this computing process is described as qubits undergo unitary transformations. Upon completion of computation, qubits are measured to gain information about the qubit states.

Therefore, to describe a quantum operation, it is necessary to identify the qubit or set of qubits to which the operation is applied. In a quantum program, each quantum instruction needs to encode both an operation to be performed and one or more qubits on which to perform the operation. In existing quantum instruction set architectures (e.g., QASM, Open QASM, QIS, etc) register operands are normally encoded in the opcode of an instruction. This scheme works for classical computing because the number of registers are very limited (e.g., 16, 32, 64, etc). However, this scheme is not scalable for quantum computing as quantum instructions will ultimately need to address a very large numbers of qubits. Consequently, encoding qubit addresses in the opcode field of quantum instructions would explode the instruction width.

As described above, in one embodiment, quantum instructions and non-quantum instructions are processed together within a shared processor pipeline. As such, the quantum instructions may rely on the same addressing modes as those available to the non-quantum instructions. The qubits in this embodiment are therefore addressed in a similar manner as non-quantum instructions which access system memory, providing a sufficiently large address space to accommodate a large number of qubits.

As illustrated in FIG. 8 , in this embodiment, the quantum engine functional units 204E include a qubit index generation unit (QIG) 802 which determines a qubit index value or qubit ID in response to one or more uops 805. One or more quantum operation units 801 process the operations specified by the uops. The qubit index value (e.g., 011 for qubit 3 in the example) is then incorporated within the codeword/command packet 606, potentially along with one or more commands generated by the quantum operation unit 801 in response to processing the uops 805.

The QIG 802 may operate in accordance with different addressing modes supported by the processor. In one embodiment, the instruction identifies one of the shared registers 321 which contains the qubit index value (sometimes also referred to as a qubit ID). It may then use the qubit index value to identify the qubit within the codeword/command packet 606 and/or perform an operation using the qubit index value to generate one or more additional qubit index values. For example, it may add the qubit ID value to an integer specified by the uop to generate a second qubit ID.

The following examples demonstrate one way in which the QIG 802 generates qubit IDs in response to uops using an x86 assembly syntax. These operations may be performed within an x86 pipeline extended to support quantum instructions. However, the same general principles may be implemented on any processor architecture.

The single qubit instruction “QIROTX [RDI], 1” applies an X gate to the qubit number stored in RDI. Thus, if RDI contains 5, the X gate is applied to qubit number 5. In this example, the QIG 802 determines the qubit ID simply by reading the value stored in RDI (which is one of the shared registers 321 in this example). In this embodiment, the RDI value was stored previously by another uop. As another example, if the architecture register RBX contains a value of 2, then the two qubit instruction “QCNOTUP [RBX+3],” applies a CNOT operation with qubit 2 (q[2]) being the control qubit and qubit 5 (q[5]) being the target qubit. The QIG interprets the [RBX+3] notation as: the ID of the control qubit is stored in RBX and the ID of the control qubit+3 is the target qubit ID. Thus, the addressing scheme is extended so that two different qubits can be addressed with a single instruction, (i.e., CNOT). In contrast, in classical computing, only one memory location is addressed per instruction.

FIG. 8 also illustrates a codeword triggered pulse generator (CTPG) 402A which includes control logic and an analog-to-digital converter for interpreting the codeword/command packet 606 to identify one or more qubits (Q3 in the example) and generate a sequence of pulses to implement the specified quantum operations. When all of the quantum operations have been performed, as specified by the program code 205C, the quantum operation circuitry 801 and QIG 802 generates a codeword/command packet 606, causing one or more MDUs 403A-B to take a measurement of one or more qubits (as specified by the QIG 802 which generates the qubits indices). As mentioned, the MDUs include analog-to-digital circuitry to convert the analog measurements to digital values, which are then processed by a quantum error correction unit 808 to detect and potentially correct errors. If valid result data has been received it may be stored within one or more of the shared registers 321 and/or accumulated with prior measurement data. In addition to error correction, the measurement can also be used for program flow control based on measurement feedback.

The quantum error correction unit 808 may implement various techniques for detecting and correcting quantum errors. For example, in one embodiment, an error decoder (within the QEC unit 808) decodes a multi-qubit measurement from the quantum processor 207 to determine whether an error has occurred and, if so, implements corrective measures (is possible). The error measurements may be taken from multiple qubits in a manner which does not disturb the quantum information in the encoded state of the qubits (e.g., using ancilla qubits). In response, the QEC unit 808 generates error syndrome data from which it may identify the errors that have occurred and implement corrective operations. In one embodiment, the error syndrome data comprises a stabilizer code such as a surface code. In some cases, the response may simply be to reinitialize the qbits and start over. In other cases, however, modifications to the quantum algorithm implemented in the quantum program code 205C can be made to stabilize the region of the quantum processor responsible for the error (e.g., where compiler 205B includes a just-in-time (JIT) compiler). In either case, the CTPGs 402A perform the underlying physical operations under the control of the codewords/command packets 606 generated by the QEFU 204E. For example, the CTPG 402A may generate electromagnetic pulses to adjust the phase of one or more qbits in accordance with the detected phase error, or to reset the phase/spin of all qbits if re-initialization is required.

Addressing qubits in a manner which is similar to how classical CPU's address memory provides the scalability characteristics/attributes required for future quantum processor implementations. In particular, the above-described embodiments provide qubit indexing which is seamlessly integrated within an existing processor ISA and scales to a large number of qubit systems. These embodiments also remove pressure from the quantum instruction opcode space by way of a quantum extension to x86 or other architectures to address the qubit space and integrate quantum operations to existing processor pipelines.

A method in accordance with one embodiment of the invention is illustrated in FIG. 9 . The method may be implemented on the architectures described above but is not limited to any particular processor or system architecture.

At 901 quantum and non-quantum instructions from runtime program code are fetched and decoded, generating quantum and non-quantum uops. At 902 an index generation unit evaluates quantum uops including register identifiers and optionally one or more values included with the uops to determine qubit index values. As described above, the indices may be generated using a variety of techniques including reading qubit index values from registers identified by the uops and generating additional qubit index values using integer values included with the uops.

At 903, the quantum execution circuitry generates a codeword specifying the quantum operations to be performed on the qubits identified by the calculated qubit index values. At 904, the quantum operations are performed on the specified qubits. At 905, qubit measurements are performed in response to another codeword generated based on additional uops. At 906, the analog measurement made on one or more of the qubits are converted to digital values. Error correction and/or flow control may then be performed based on the resulted digital result values stored in a register file of the processor.

FIG. 10 illustrates a typical quantum computer arrangement with error detection and correction. The illustrated example includes a quantum computer runtime 1001 (e.g., implemented in QASM program code), which is executed by a quantum execution pipeline 1005 of a quantum execution unit 1002. By way of example, and not limitation, the quantum execution unit 1002 may be an application-specific integrated circuit ASIC, a general purpose processor, or a programmable functional unit for executing quantum instructions.

In response to execution of the quantum program code, the quantum execution pipeline 1005 transmits commands to a qubit drive controller 1010 which performs the physical quantum operations on the quantum chip 1020. Depending on the implementation, this may be accomplished by a sequence of RF pulses to manipulate the qubits Q0-Q15 of the quantum chip 1020.

After all or a certain number of program operations have completed, a measurement unit 1015 reads/estimates the quantum state of one or more of the qubits Q0-Q15 and provides the measurement results to a decoding/error correction unit 1016 which decodes the measurements using error correction decoding techniques. For example, the decoding/error correction unit 1016 decodes a multi-qubit measurement from the quantum processor 1020 to determine whether an error has occurred and, if so, implements corrective measures if possible. The error measurements may be taken from multiple qubits in a manner which does not disturb the quantum information in the encoded state of the qubits (e.g., using ancilla qubits). In response, error syndrome data may be generated from which errors and corrective operations may be identified. In one embodiment, the error syndrome data comprises a stabilizer code such as a surface code. In some cases, the response may simply be to reinitialize the qbits Q0-Q15 and start over. In other cases, however, modifications to the quantum algorithm may be implemented in the quantum program code 1001.

The decoded/corrected results are provided to the quantum execution unit 1002 for further processing in accordance with the quantum runtime 1001. The typical operational flow of current quantum computer designs based on a fixed cycle time for each quantum operation executed by the quantum execution pipeline 1005 and each measurement taken by the measurement unit 1015.

FIG. 11 illustrates one embodiment of a quantum error correction cycle which may be implemented by the architectures described herein. At 1101 the logical qubit state of the system is initialized. For example, if electron spin is used as the quantum state, then electrons within the quantum system may be prepared (e.g., initialized to a particular spin orientation and/or entangled using electromagnetic control signals from the quantum controller).

At 1102, the state of the quantum system evolves in response to additional electromagnetic inputs specified by the quantum runtime 1001 and implemented by the quantum controller 1010. For example, different sets of qubits, including ancilla qubits, may be entangled and manipulated in accordance with the quantum runtime 1001.

At 1103, a measurement of the quantum system is taken. For example, the current spin of one of the entangled electrons may be measured. The system may subsequently be re-initialized prior to the next measurement (i.e., given that taking a measurement or learning any information about the quantum system disrupts the quantum state). The physical qubits may be periodically measured during each error correction cycle.

At 1104 error detection/classification is performed on the measured results to determine whether an error has occurred. The error cycle completes with an error correction operation at 1105 using a specified set of codes, which attempts to correct any detected errors.

Error Reduction in Distributed Quantum Systems Via Fusing-and-Decomposing Gates

Scaling up quantum computers will require communication between quantum modules. As used herein, the term “module” refers to a core, chiplet, die, package, system, or other distinct collection of qubits. This requirement for scaling may be true even within 10 years, as even near-term quantum computers may consist of multiple interconnected silicon quantum dot “chiplets,” ion traps, superconductor arrays, or any other type of interconnected hardware.

Such inter-module communication, however, can lead to lower-fidelity quantum computing given that inter-module operations are more error-prone than intra-module operations. In addition, more communication leads to more idling time which increases decoherence between qubit states.

Currently, there are only partial solutions to this problem which focus primarily on reordering qubit indices using different optimization algorithms. However, these techniques perform no modification to the quantum gate sequence itself. As a result, the possible routes for reducing communication-related error are limited.

To address these limitations, the embodiments of the invention described below include various techniques to reduce quantum error by reducing the amount of inter-module communication required. In particular, these embodiments implement “fuse-and-decompose” operations in a quantum computing compiler in which many quantum gates are “fused” into one large “unitary” operation, and decomposed into a different sequence of gates that reduce overall algorithm error and/or reduce the complexity of classical algorithmic steps such as optimization and synchronization. As discussed, these techniques scale to a large number of quantum modules.

Referring to FIGS. 12A-B, near and mid-term quantum computing will require communication between quantum modules 1201-1206, which may be chiplets, cores, or any other distinct collection of qubits. FIG. 12A illustrates a plurality of quantum modules 1201-1206 connected via communication interconnects 1210 to form a larger quantum system 1200. FIG. 12B illustrates an example of the gate-level interconnections between a first quantum module 1251 and a second quantum module 1252. In this specific example, the quantum modules 1251-1252 include single-qubit U-gates, used for the purpose of illustration. It should be noted, however, that the underlying principles of the invention may be implemented on modules having various other qubit gate types.

FIGS. 13A-B and 14A-D illustrate an overview of the fuse-and-decompose techniques described herein. As shown in FIG. 13A, a sequence of consecutive gates are identified that are near the boundary of the module 1301 and that operate on no more than X qubits, where X is a pre-defined threshold. Next, unitary generation logic 1310 combines the sequence of gates into one large unitary matrix 1302.

Referring to FIG. 13B, decomposition logic 1310 then decomposes this unitary 1302 into multiple alternative gate sequences 1320. An exact gate sequence may be generated for each decomposition (e.g., 1321) or approximate gate sequence may be used as described below with respect to FIGS. 14A-B.

In the following example, the fuse-and-decompose techniques are implemented on an example 2-dimensional grid topology, highlighting how fuse-and-decompose scales up in a parallelized way on a many-module device.

Four modules 1401-1404 are illustrated in FIG. 14A, each having a plurality of qubits 1410. The goal is to reduce communication between the modules 1401-1404 by reducing gates that cross the inter-module line 1440.

As shown in FIG. 14B, a first sequence of operations (Subroutine 1) moves the quantum gates around such that they avoid crossing both the inter-module line 1440 and the cluster line 1450. In particular, for a set of clock cycles, a swap sequence is performed that minimizes the number of gates that cross these lines. The cluster line 1450 is used in order to cluster the gates together. Fewer gates crossing the cluster line 1450 ensures that as many gates as possible may be used for fuse-decompose operations.

These operations may be optional, but can allow more clock cycles in a row to be fused. It is trivial to parallelize the determination of this SWAP sequence over multiple qubits and over multiple clock cycles.

Referring to FIG. 15 , a second sequence of operations (Subroutine 2) includes two nested steps. First, partition generation logic 1550 identifies multiple partitions of qubits (e.g., 1510, 1511). Each partition should be no larger than X qubits, where X is a pre-determined number (e.g., 4, 6, 8, etc). Second, for each of these partitions 1510, 1511 fuse-and-decompose logic 1560-1561 performs the fuse-and-decompose operations described above with respect to FIGS. 13A-B. The fuse-and-decompose operations may be performed over multiple clock cycles. Then selection logic (not shown) selects the decomposition result with the lowest cost function, C_(min).

The embodiments of the invention can use various different cost functions. For example, the cost function may be a function of one or more of: decoherence time, change in execution time, local 2-qubit gate errors, inter-module 2-qubit gate errors, change in local gate count, change in inter-module gate count, and approximate simulations of the new circuit. Additional examples are provided below. FIG. 16A is a course-grained schematic of one embodiment of the invention in the many-module case. The optimization operations alternate between subroutine 1 (SR1) and subroutine 2 (SR2), where subroutine 1 is the optimized swap sequence (see, e.g., FIG. 14B and associated text). Clock cycles are indicated by squares labeled FIG. 16B provides an example of the positions of the quantum gates during clock cycle 1 and clock cycle 2. Subroutine 2 is the parallelized analysis for the choice of partition and fuse-and-decompose operations, which are performed on the i'th “period” of an arbitrary number of clock cycles R_(i) (R₁ and R₂ clock cycles are shown for illustration purposes). The final cost function is the sum of C_(min) over all periods. In some implementations, the sequence may be further optimized by varying the periods, R_(i).

Due to the many parameters and hyperparameters over which optimization may be performed, these techniques can be made arbitrarily cheap or expensive. For example, a user may choose to search only a small set of decompositions in some cases. Additionally, we note that a substantial compilation cost will often be worth it for even a modest reduction in quantum error.

The embodiments of the invention may also be applied internally to a module. For example, the fuse-and-decompose techniques described here may be used to decrease the depth or error of an arbitrary quantum circuit, even if the quantum device includes a single quantum module.

Moreover, the embodiments of the invention are applicable to both near-term and long-term quantum computing hardware. For near-term multi-module hardware, the embodiments described here may be used to reduce communication for the purpose of improving fidelity. Conversely, in the long-term, the primary focus of these techniques may change to reducing quantum simulation time, including for both quantum and classical subroutines (where classical subroutines include compilation steps and execution synchronization). In the case of long-term error-corrected hardware, the cost function would primarily consider the reduction in overall simulation time.

A method in accordance with one embodiment of the invention is illustrated in FIG. 17 . The method may be implemented on the architectures described below, but is not limited to any particular quantum processing architecture.

At 1701 a set of quantum modules are interconnected. As mentioned, each of the quantum modules may be individual quantum processors such as chiplets or multi-chip modules. At 1702 a swap sequence of operations is performed to minimize boundary-adjacent gates (e.g., to reduce the amount of inter-module communication). At 1703, sets of qubits are selected over which to fuse gates. For example, sets of N qubits may be selected (e.g., where N=4, 6, 8, etc). At 1704, gates are fused over each set of qubits and at 1705, decomposed into multiple alternative gate sequences.

At 1706 a cost function is applied to each of the alternative gate sequences. The gate sequence with the smallest cost function is then selected.

The following are illustrative examples of cost functions. Note, however, that the underlying principles of the invention are not limited to any particular cost function or set of cost functions.

Example cost function 1: Fast criterion with exact decompositions.

$C = {\frac{{\Delta S} + {\Delta R}}{\tau_{decoh}} + {\Delta M_{inter}\epsilon_{inter}} + {\Delta M_{intra}\epsilon_{intra}}}$

-   -   τ_(decoh)—qubit decoherence time     -   ε_(inter)—error of chip-to-chip 2q gates     -   ε_(intra)—error of intra-chip 2q gates     -   ΔM_(inter)—change in #chip-to-chip 2q gates     -   ΔM_(intra)—change in #intra-chip 2q gates     -   ΔS—execution time change due to circuit depth increase     -   ΔR—execution time change due to communications increase

Example cost function 2: Fast criterion with approximate decompositions.

$C = {\frac{{\Delta S} + {\Delta R}}{\tau_{decoh}} + {\Delta M_{inter}\epsilon_{inter}} + {\Delta M_{intra}\epsilon_{intra}} + {❘{U - \overset{\sim}{U}}❘}}$

-   -   τ_(decoh)—qubit decoherence time     -   ε_(inter)—error of chip-to-chip 2q gates     -   ε_(intra)—error of intra-chip 2q gates     -   ΔM_(inter)—change in #chip-to-chip 2q gates     -   ΔM_(intra)—change in #intra-chip 2q gates     -   ΔS—execution time change due to circuit depth increase     -   ΔR—execution time change due to communications increase     -   Ū=approximate unitary     -   |ω|=matrix norm

Example cost function 3: Tensor network criterion. This implementation applies equally to both exact-decomposition and approximate-decomposition methods.

1. Construct three N-qubit tensor networks for: (a) the noise-free circuit ψ_(NF), (b) the original noisy circuit ψ_(orig), and (c) a candidate approximate circuit ψ_(cand,i). Include decoherence and error-prone gates by introducing “noise gates” and/or “error gates”.

2. The initial state is arbitrary—it may be chosen as equal superposition, density matrix of the plausible input subspace, or other user-defined choice.

3. Contract the networks in order to calculate the cost function Ci=|<ψ_(NF)|ψ_(orig)>|−|<ψ_(NF)|ψ_(cand,i)>|.

To speed up calculation, intermediate singular value decompositions (SVDs) may be used for a less precise tensor network calculation. This methodology would be readily understood by those of ordinary skill in the art (e.g., theoreticians in the field of quantum computing).

The techniques described above are also applicable to any arbitrary hardware types, including, but not limited to arrays of quantum dots on the same silicon wafer (Communication type: on-chip interconnect); superconducting chips in different fridges (Communication type: photonic interconnect); and ion trap qubit arrays in different traps (Communication type: photonic interconnect).

In the above detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments. Terms like “first,” “second,” “third,” etc. do not imply a particular ordering, unless otherwise specified.

Examples

The following are example implementations of different embodiments of the invention.

Example 1. A method comprising: combining a group of quantum gates to form at least one unitary operation; decomposing the unitary operation into multiple alternative gate sequences comprising either exact gate sequences or approximate gate sequences; and evaluating the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.

Example 2. The method of example 1 wherein the group of quantum gates comprises a first subset of a plurality of quantum gates spanning multiple interconnected quantum modules.

Example 3. The method of example 2 further comprising: partitioning the plurality of quantum gates into a plurality of subsets of quantum gates including the first subset; combining the quantum gates in each subset to form a separate unitary operation; decomposing each of the unitary operations into multiple alternative gate sequences; and evaluating the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.

Example 4. The method of example 3 wherein evaluating further comprises: adding cost function values determined from each of the multiple alternative gate sequences decomposed from each of the unitary operations to generate a plurality of cost values; and selecting a combination of gate sequences associated with a minimum of the cost values.

Example 5. The method of example 1 wherein the cost function is based on one or more of: decoherence time, change in execution time, local 2-qubit gate errors, inter-module 2-qubit gate errors, change in local gate count, change in inter-module gate count, and approximate simulations of a circuit.

Example 6. The method of example 3 further comprising: identifying the group of quantum gates within a first module to be used to form the unitary operation, including identifying a sequence of consecutive gates within the first module that are within a specified proximity of a boundary of the first module and that operate on no more than X qubits, where X is a pre-defined threshold.

Example 7. The method of example 6 wherein identifying further comprises: moving the group of quantum gates to different positions within the first module to identify an arrangement which minimizes or reduces a number of interconnections with quantum gates in a second module.

Example 8. The method of example 7 wherein the first and second modules comprise quantum processors each comprising a plurality of qubits.

Example 9. The method of example 7 wherein the first and second modules each comprise arrays of quantum dots on silicon wafers; superconducting chips in different fridges; and/or ion trap qubit arrays in different traps.

Example 10. The method of example 1 wherein the group of quantum gates are included in a single quantum module.

Example 11. An apparatus comprising: a quantum module comprising a plurality of qubits; unitary generation logic to combine a group of quantum gates to form at least one unitary operation; decomposition logic to decompose the unitary operation into multiple alternative gate sequences comprising either exact gate sequences or approximate gate sequences; and selection logic to evaluate the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.

Example 12. The apparatus of example 11 wherein the quantum module comprises one of a plurality of interconnected quantum modules and wherein the group of quantum gates comprises a first subset of a plurality of quantum gates at least some of which span the interconnected quantum modules.

Example 13. The apparatus of example 12 further comprising: partitioning logic to partition the plurality of quantum gates into a plurality of subsets of quantum gates including the first subset; wherein the unitary logic is to combine the quantum gates in each subset to form a separate unitary operation, wherein the decomposition logic is to decompose each of the unitary operations into multiple alternative gate sequences; and wherein the selection logic is to evaluate the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.

Example 14. The apparatus of example 13 further comprising: cost summation logic to add cost function values determined from each of the multiple alternative gate sequences decomposed from each of the unitary operations to generate a plurality of cost values; and wherein the selection logic is to select a combination of gate sequences associated with a minimum of the cost values.

Example 15. The apparatus of example 11 wherein the cost function is based on one or more of: decoherence time, change in execution time, local 2-qubit gate errors, inter-module 2-qubit gate errors, change in local gate count, change in inter-module gate count, and approximate simulations of a circuit.

Example 16. The apparatus of example 13 wherein the partitioning logic is to identify the group of quantum gates within a first module to be used to form the unitary operation, including identifying a sequence of consecutive gates within the first module that are within a specified proximity of a boundary of the first module and that operate on no more than X qubits, where X is a pre-defined threshold.

Example 17. The apparatus of example 16 wherein to identify the group of quantum gates within the first module, the partitioning logic is to move the group of quantum gates to different positions within the first module to identify an arrangement which minimizes or reduces a number of interconnections with quantum gates in a second module.

Example 18. The apparatus of example 17 wherein the first and second modules comprise quantum processors, each comprising a plurality of qubits.

Example 19. The apparatus of example 17 wherein the first and second modules each comprise arrays of quantum dots on silicon wafers; superconducting chips in different fridges; and/or ion trap qubit arrays in different traps.

Example 20. A machine-readable medium having program code stored thereon which, when executed by a qubit controller, causes the operations of: combining a group of quantum gates to form at least one unitary operation; decomposing the unitary operation into multiple alternative gate sequences comprising either exact gate sequences or approximate gate sequences; and evaluating the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.

Example 21. The machine-readable medium of example 20 wherein the group of quantum gates comprises a first subset of a plurality of quantum gates spanning multiple interconnected quantum modules.

Example 22. The machine-readable medium of claim 21 further comprising program code to cause the machine to perform the operations of: partitioning the plurality of quantum gates into a plurality of subsets of quantum gates including the first subset; combining the quantum gates in each subset to form a separate unitary operation; decomposing each of the unitary operations into multiple alternative gate sequences; and evaluating the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.

Example 23. The machine-readable medium of example 22 wherein evaluating further comprises: adding cost function values determined from each of the multiple alternative gate sequences decomposed from each of the unitary operations to generate a plurality of cost values; and selecting a combination of gate sequences associated with a minimum of the cost values.

Example 24. The machine-readable medium of example 20 wherein the cost function is based on one or more of: decoherence time, change in execution time, local 2-qubit gate errors, inter-module 2-qubit gate errors, change in local gate count, change in inter-module gate count, and approximate simulations of a circuit.

Example 25. The machine-readable medium of example 22 further comprising: identifying the group of quantum gates within a first module to be used to form the unitary operation, including identifying a sequence of consecutive gates within the first module that are within a specified proximity of a boundary of the first module and that operate on no more than X qubits, where X is a pre-defined threshold.

Example 26. The machine-readable medium of example 25 wherein identifying further comprises: moving the group of quantum gates to different positions within the first module to identify an arrangement which minimizes or reduces a number of interconnections with quantum gates in a second module.

Example 27. The machine-readable medium of example 26 wherein the first and second modules comprise quantum processors each comprising a plurality of qubits.

Example 28. The machine-readable medium of example 26 wherein the first and second modules each comprise arrays of quantum dots on silicon wafers; superconducting chips in different fridges; and/or ion trap qubit arrays in different traps.

Example 29. The machine-readable medium of example 20 wherein the group of quantum gates are included in a single quantum module.

For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation “A/B/C” means (A), (B), and/or (C).

The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.

Embodiments of the invention may include various steps, which have been described above. The steps may be embodied in machine-executable instructions which may be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, these steps may be performed by specific hardware components that contain hardwired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.

As described herein, instructions may refer to specific configurations of hardware such as application specific integrated circuits (ASICs) configured to perform certain operations or having a predetermined functionality or software instructions stored in memory embodied in a non-transitory computer readable medium. Thus, the techniques shown in the figures can be implemented using code and data stored and executed on one or more electronic devices (e.g., an end station, a network element, etc.). Such electronic devices store and communicate (internally and/or with other electronic devices over a network) code and data using computer machine-readable media, such as non-transitory computer machine-readable storage media (e.g., magnetic disks; optical disks; random access memory; read only memory; flash memory devices; phase-change memory) and transitory computer machine-readable communication media (e.g., electrical, optical, acoustical or other form of propagated signals—such as carrier waves, infrared signals, digital signals, etc.).

In addition, such electronic devices typically include a set of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input/output devices (e.g., a keyboard, a touchscreen, and/or a display), and network connections. The coupling of the set of processors and other components is typically through one or more busses and bridges (also termed as bus controllers). The storage device and signals carrying the network traffic respectively represent one or more machine-readable storage media and machine-readable communication media. Thus, the storage device of a given electronic device typically stores code and/or data for execution on the set of one or more processors of that electronic device. Of course, one or more parts of an embodiment of the invention may be implemented using different combinations of software, firmware, and/or hardware. Throughout this detailed description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without some of these specific details. In certain instances, well known structures and functions were not described in elaborate detail in order to avoid obscuring the subject matter of the present invention. Accordingly, the scope and spirit of the invention should be judged in terms of the claims which follow. 

What is claimed is:
 1. A method comprising: combining a group of quantum gates to form at least one unitary operation; decomposing the unitary operation into multiple alternative gate sequences comprising either exact gate sequences or approximate gate sequences; and evaluating the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.
 2. The method of claim 1 wherein the group of quantum gates comprises a first subset of a plurality of quantum gates spanning multiple interconnected quantum modules.
 3. The method of claim 2 further comprising: partitioning the plurality of quantum gates into a plurality of subsets of quantum gates including the first subset; combining the quantum gates in each subset to form a separate unitary operation; decomposing each of the unitary operations into multiple alternative gate sequences; and evaluating the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.
 4. The method of claim 3 wherein evaluating further comprises: adding cost function values determined from each of the multiple alternative gate sequences decomposed from each of the unitary operations to generate a plurality of cost values; and selecting a combination of gate sequences associated with a minimum of the cost values.
 5. The method of claim 1 wherein the cost function is based on one or more of: decoherence time, change in execution time, local 2-qubit gate errors, inter-module 2-qubit gate errors, change in local gate count, change in inter-module gate count, and approximate simulations of a circuit.
 6. The method of claim 3 further comprising: identifying the group of quantum gates within a first module to be used to form the unitary operation, including identifying a sequence of consecutive gates within the first module that are within a specified proximity of a boundary of the first module and that operate on no more than X qubits, where X is a pre-defined threshold.
 7. The method of claim 6 wherein identifying further comprises: moving the group of quantum gates to different positions within the first module to identify an arrangement which minimizes or reduces a number of interconnections with quantum gates in a second module.
 8. The method of claim 7 wherein the first and second modules comprise quantum processors each comprising a plurality of qubits.
 9. The method of claim 7 wherein the first and second modules each comprise arrays of quantum dots on silicon wafers; superconducting chips in different fridges; and/or ion trap qubit arrays in different traps.
 10. The method of claim 1 wherein the group of quantum gates are included in a single quantum module.
 11. An apparatus comprising: a quantum module comprising a plurality of qubits; unitary generation logic to combine a group of quantum gates to form at least one unitary operation; decomposition logic to decompose the unitary operation into multiple alternative gate sequences comprising either exact gate sequences or approximate gate sequences; and selection logic to evaluate the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.
 12. The apparatus of claim 11 wherein the quantum module comprises one of a plurality of interconnected quantum modules and wherein the group of quantum gates comprises a first subset of a plurality of quantum gates at least some of which span the interconnected quantum modules.
 13. The apparatus of claim 12 further comprising: partitioning logic to partition the plurality of quantum gates into a plurality of subsets of quantum gates including the first subset; wherein the unitary logic is to combine the quantum gates in each subset to form a separate unitary operation, wherein the decomposition logic is to decompose each of the unitary operations into multiple alternative gate sequences; and wherein the selection logic is to evaluate the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.
 14. The apparatus of claim 13 further comprising: cost summation logic to add cost function values determined from each of the multiple alternative gate sequences decomposed from each of the unitary operations to generate a plurality of cost values; and wherein the selection logic is to select a combination of gate sequences associated with a minimum of the cost values.
 15. The apparatus of claim 11 wherein the cost function is based on one or more of: decoherence time, change in execution time, local 2-qubit gate errors, inter-module 2-qubit gate errors, change in local gate count, change in inter-module gate count, and approximate simulations of a circuit.
 16. The apparatus of claim 13 wherein the partitioning logic is to identify the group of quantum gates within a first module to be used to form the unitary operation, including identifying a sequence of consecutive gates within the first module that are within a specified proximity of a boundary of the first module and that operate on no more than X qubits, where X is a pre-defined threshold.
 17. The apparatus of claim 16 wherein to identify the group of quantum gates within the first module, the partitioning logic is to move the group of quantum gates to different positions within the first module to identify an arrangement which minimizes or reduces a number of interconnections with quantum gates in a second module.
 18. The apparatus of claim 17 wherein the first and second modules comprise quantum processors, each comprising a plurality of qubits.
 19. The apparatus of claim 17 wherein the first and second modules each comprise arrays of quantum dots on silicon wafers; superconducting chips in different fridges; and/or ion trap qubit arrays in different traps.
 20. A machine-readable medium having program code stored thereon which, when executed by a qubit controller, causes the operations of: combining a group of quantum gates to form at least one unitary operation; decomposing the unitary operation into multiple alternative gate sequences comprising either exact gate sequences or approximate gate sequences; and evaluating the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.
 21. The machine-readable medium of claim 20 wherein the group of quantum gates comprises a first subset of a plurality of quantum gates spanning multiple interconnected quantum modules.
 22. The machine-readable medium of claim 21 further comprising program code to cause the machine to perform the operations of: partitioning the plurality of quantum gates into a plurality of subsets of quantum gates including the first subset; combining the quantum gates in each subset to form a separate unitary operation; decomposing each of the unitary operations into multiple alternative gate sequences; and evaluating the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.
 23. The machine-readable medium of claim 22 wherein evaluating further comprises: adding cost function values determined from each of the multiple alternative gate sequences decomposed from each of the unitary operations to generate a plurality of cost values; and selecting a combination of gate sequences associated with a minimum of the cost values.
 24. The machine-readable medium of claim 20 wherein the cost function is based on one or more of: decoherence time, change in execution time, local 2-qubit gate errors, inter-module 2-qubit gate errors, change in local gate count, change in inter-module gate count, and approximate simulations of a circuit.
 25. The machine-readable medium of claim 22 further comprising: identifying the group of quantum gates within a first module to be used to form the unitary operation, including identifying a sequence of consecutive gates within the first module that are within a specified proximity of a boundary of the first module and that operate on no more than X qubits, where X is a pre-defined threshold.
 26. The machine-readable medium of claim 25 wherein identifying further comprises: moving the group of quantum gates to different positions within the first module to identify an arrangement which minimizes or reduces a number of interconnections with quantum gates in a second module.
 27. The machine-readable medium of claim 26 wherein the first and second modules comprise quantum processors each comprising a plurality of qubits.
 28. The machine-readable medium of claim 26 wherein the first and second modules each comprise arrays of quantum dots on silicon wafers; superconducting chips in different fridges; and/or ion trap qubit arrays in different traps.
 29. The machine-readable medium of claim 20 wherein the group of quantum gates are included in a single quantum module. 